Implementation of 128/256 bit data bus microprocessor core on FPGA

Abstract

This paper shows the implementation of a large data bus size microprocessor core of 128/256 bits on an Altera Stratix 2 FPGA using a superscalar architecture of 3 parallel pipes with 4 stage pipeline as shown in Figure 1. The system level implementation utilizing the implemented microprocessor core on FPGA is shown in Figure 2. The micro-architecture of the microprocessor core architecture of Figure 1 is implemented using four pipe stages of fetch, decode, execute and writeback with a shared register file for all 3 parallel pipes, as shown in Figure 3.