8-bits X 8-bits modified Booth 1’s complement multiplier

Abstract

With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed, low power, and compact VLSI implementation. This project focuses on speed performance of the Modified Baugh-Wooley Two’s Complement Signed Multiplier. Three methods to improve speed performance of the multiplier – reduce the number of partial products and accelerate the accumulation have been discussed in literature view. For Modified Baugh-Wooley Two’s Complement Signed Multiplier the speed is improved by reducing the partial products and then summing these partial products using Carry Save Adder. The schematic design as well as speed performance analysis of this multiplier is done using Altera’s Quartus II Software and speed obtained on EPF10K70.