High speed 8-bits x 8-bits Wallace Tree multiplier

Abstract

This final year project (FYP) is to analyze the design of Wallace Tree multiplier. For simplicity, unsigned operands are chosen and main focus on the short word widths commonly used in most applications: an 8-bit multiplier. Before this era, multiplier that used low power supply or multiplier that has low power dissipation is always being the choice to be used. However, now, there is one more important feature that a multiplier should have that is high-speed to solve multiplication problems. Therefore, this FYP studied that an 8-bits x 8-bits Wallace Tree multiplier is one of the high speed multiplier among the other types of multiplier. The analysis covers from the schematic design until the source code design of the multiplier. Design entry that is used for this project is the Verilog hardware description language (HDL) using the Altera Quartus II software. From the results achieved, it shows that the conventional circuit produces the maximum speed of 14.99 MHz or maximum delay of 66.7 nanoseconds to complete one process of 8-bits x 8-bits multiplication. After upgrading the conventional Wallace Tree into pipelined, by adding D flip-flop stages, the speed has increased to 54.05 MHz and the maximum delay has decreased to 18.3 nanoseconds. Finally, after completed the analysis of the Wallace Tree multiplier, it has been proven that the pipelining method could increased the speed of the multiplier.