Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications

Abstract

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plans are to instantiate a good design and modify it for low power and speed and prepare its layout using TSMC 0.18um in Mentor Graphic. I have used a unique technique for power reduction in Wallace tree. The design also proposed a method to calculate 2’s complement of multiplicand for final Partial Product if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The total designed of MAC unit consumed about 15.3438nW and power delay product is approximately 0.056fJ. Hence, it proven that this MAC unit design had saved power consumption and has also a very high speed performance with 273.97MHz.