Performance evaluation of SRAM-PUF based on 7-nm, 10-nm and 14-nm FinFET technology nodes

Abstract

As complementary metal-oxide semiconductor (CMOS) technology continues to scale down to ultra-deep submicron (UDSM) technology, the planar metal-oxide semiconductor field-effect transistor (MOSFET) structure reaches its limit. As the channel length shrinks, the gate no longer has full control over the channel which is not desirable. The subthreshold leakage from drain to source increases as the impact over the lost control of the MOS gate terminal, and further increase the total power consumption. To ensure the continuation of CMOS scaling and to overcome the aforementioned issues, the new MOS structure which is known as fin field-effect transistor (FinFET) is introduced. On the other hand, Physical Unclonable Function (PUF) is a promising hardware-fingerprinting technology that can exploit the intrinsic process variations of CMOS technology and manifest them into unique and random binary responses. These responses can be used as a cryptographic key or device specific identifier. Nevertheless, FinFET introduces an unknown impact of its process variations towards the performance of a particular PUF. In this paper, the suitability of the FinFET technology node for a PUF as a device-specific identifier or secret key is evaluated. One of the memory-PUFs, known as static random-access memory PUF (SRAM-PUF) has been used as a case study. Three different FinFET technology nodes which are 14-nm, 10-nm, and 7-nm have been evaluated. Our findings show that the uniqueness and uniformity of SRAM-PUF still hold, closely distributed at around an ideal value of 50%. The average reliability under temperature variations of -40ᴼC to 85ᴼC is approximately about 98%. The reliability of SRAM-PUF responses under the Vdd ramp-up time variations has no significant impact although showing declining patterns at fast ramp-up time. It can be concluded that FinFET technology shows no surprises on SRAM-PUF performances.