| dc.contributor.author | Tamayanti, Ramasandram | |
| dc.date.accessioned | 2016-06-16T06:59:45Z | |
| dc.date.available | 2016-06-16T06:59:45Z | |
| dc.date.issued | 2015-06 | |
| dc.identifier.uri | http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42079 | |
| dc.description | Access is limited to UniMAP community. | en_US |
| dc.description.abstract | This project is about Prototype of 16 bit CPU on FPGA. This prototyping of
CPU uses the Very High Speed Integrated Circuit Hardware Description Language
(VHDL) and the output will be displayed on the FPGA board. Few steps are implemented in this project which is the fetch, decode, execute and store. Besides that there are few components required to develop the CPU which are the Control Unit, ALU, Storage unit, datapath and also registers. The Datapath unit and Control unit plays
the main role in this project. The input will send the data and instruction in 16 bit to the registers. The VHDL code will be written into the Quartus software and then executed.
The result was displayed on the FPGA board. Finally this project has successfully
develop prototyping 16-bit CPU on FPGA with hardware working as per the simulation. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Universiti Malaysia Perlis (UniMAP) | en_US |
| dc.subject | 16 bit CPU | en_US |
| dc.subject | Central Processing Unit (CPU) | en_US |
| dc.subject | Central Processing Unit (CPU) -- Design and construction | en_US |
| dc.subject | VHDL (Computer hardware description language) | en_US |
| dc.title | Prototype of 16 BIT CPU on FPGA | en_US |
| dc.type | Learning Object | en_US |
| dc.contributor.advisor | Dr Phak LenEh Kan | en_US |
| dc.publisher.department | School of Computer and Communication Engineering | en_US |
