Uda Hashim, Prof. Ts. Dr.: Recent submissions
Now showing items 221-240 of 243
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Nanowire formation for single electron transistor using SEM based Electron Beam Lithography (EBL) technique: Positive tone vs negative tone e-beam resist
(Nano Science and Technology Institute, 2006)Experimental studies of nanowires formation are carried out by using Scanning Electron Microscope Based Electron Beam Lithography (EBL) Technique with critical dimensions in less than 100nm. In order to complete the design ... -
A systematic dry etching process for profile control of quantum dots and nanoconstrictions
(Elsevier B.V., 2007-08)In essence, quantum dot dimensions and others can be laterally and vertically defined by using either bottom up or top down methods respectively. In fabrication that uses top down method, etch process hold a chief role. ... -
Reproducibility of silicon single electron quantum dot transistor
(Nano Science and Technology Institute, 2006)In principle, based on the form of tunnel junction, single electron transistor (SET) can be classified into four types, i.e. nanowire SET, quantum dot SET, nanotube SET and point contact SET. Another classification is SET ... -
Designing of masks for quantum dot single electron transistor fabrication using E-beam nanolithography
(Nano Science and Technology Institute, 2007)Quantum dot single electron transistor (QD SET) is able to be fabricated through a joint technique of e-beam lithography (EBL), pattern dependent oxidation (PADOX) and high density plasma etching. In this research, we have ... -
Borophosphosilicate glass (BPSG) reflow characterization for submicron CMOS technology
(Universiti Kebangsaan Malaysia, 2007)This paper involves the planarization of borophosphosilicate glass (BPSG) film using a new recipe for annealing process to improve the borophosphosilicate glass (BPSG) film flatness after reflow. This improvement is for ... -
Design of 100nm single-electron transistor (SET) by 2D TCAD simulation
(Institute of Electrical and Electronics Engineering (IEEE), 2006)One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, ... -
An estimation of the energy and exergy efficiencies for the energy resources consumption in the transportation sector in Malaysia
(Elsevier Ltd., 2007-08)The purpose of this work is to apply the useful energy and exergy analysis models for different modes of transport in Malaysia and to compare the result with a few countries. In this paper, energy and exergy efficiencies ... -
Effect of alignment mark architecture on alignment signal behavior in advanced lithography
(Universiti Malaya, 2007)Alignment mark architecture is divided into two types, which depending on where the mark is defined. Alignment mark that is defined through the contact masking steps is known as contact mark and alignment mark that is ... -
A simple oxidation technique for quantum dot dimension shrinkage and tunnel barriers generation
(Elsevier B.V., 2007-05)The tunnel barriers generation and the quantum dot size shrinkage play a significant role in single-electron transistor (SET) fabrication. Because the numerically etch indicators were not found, the technical indicators, ... -
The characterization of power supply noise for optical mouse sensor
(Institute of Electrical and Electronics Engineering (IEEE), 2006)The induced power supply noise (sinusoidal waveform) that injected to Vdd pin will cause unwanted spike at the positive amplitude and negative amplitude to the DC input voltage. At certain limit this spike will cause the ... -
Fabrication and characterization of Si quantum dots and SiO2 tunnel barriers grown by a controlled oxidation process
(IOP Publishing Ltd, 2008-01-29)The control of the growth of silicon dioxide (SiO2) and the formation of quantum dots (QDs) play an important role in the fabrication of single-electron transistors (SETs). In this work, SET structures were fabricated using ... -
Nano patterning of cone dots and nano constrictions of negative e-beam resist for single electron transistor fabrication
(Springer New York, 2007-12)We present an optimization of nano dot of negative tone e-beam resist which is a very important step in single electron transistor fabrication process. The optimum design of dot and nano constriction plays a significant ... -
Characterization of robust alignment mark to improve alignment performance
(Institute of Electrical and Electronics Engineering (IEEE), 2006)Overlay requirement is one of the biggest obstacles in achieving a very small feature. With the continued growth of small feature size, overlay requirement becomes tighter. Such a tight requirement requires a very high ... -
Alignment mark architecture effect on alignment signal behavior in advanced lithography
(Institute of Electrical and Electronics Engineering (IEEE), 2006)The downscaling of CMOS technology becomes a challenge to the scanner alignment system since overlay and alignment accuracy becomes tighter. Such a tight overlay requirement requires a very stable alignment performance. A ... -
Characteristics of Serial Peripheral Interfaces (SPI) timing parameters for optical mouse sensor
(Institute of Electrical and Electronics Engineering (IEEE), 2006)In this paper we report the characterizations results of Serial Peripheral Interface (SPI) timing parameters for optical mouse sensor. SPI is an interface that facilitates the transfer of synchronous serial data. It supports ... -
A new Microelectronic Engineering degree curriculum in KUKUM
(Association of Engineering Education in South East Asia and the Pacific, 2005-12-08)This paper presents the development and implementation of a new curriculum at the Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM). The curriculum is specifically developed for the Bachelor of Engineering Degree program ... -
The effect of temperature, pH and exposure time to Electroless Nickel Deposition for Under Bump Metallurgy (UBM)
(Universiti Putra Malaysia (UPM), 2005-12-06)The low cost deposition of under bump metallurgy (UBM) method presented in this paper is based on electroless nickel immersion gold (ENIG) bumping process. The study is focuses on the effect of temperature, pH and exposure ... -
Nanotechnology development in Malaysia: current status and implementation strategy
(Universiti Malaysia Perlis, 2008-12-05)Nano-technology development needs all the support it could get to ensure the technology is being leveled up and benefits all mankind. Malaysia has started it own micro-technology and nano-technology development since the ... -
Under Bump Metallurgy (UBM)-a technology review for flip chip packaging
(Department of Mechanical Engineering, University Malaya, 2007)Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size ... -
The effects of multiple zincation process on Aluminum Bond Pad surface for Electroless Nickel Immersion Gold deposition
(American Society of Mechanical Engineers (ASME), 2006-09)This paper reports the effects of a multiple zincation processon the Al bond pad surface prior to electroless nickel immersion gold deposition. The study of multiple zincation comprises the surface topogtaphy and morphology ...