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dc.contributor.authorRizalafande, Che Ismail
dc.contributor.authorBeckett, P
dc.date.accessioned2010-01-01T07:12:04Z
dc.date.available2010-01-01T07:12:04Z
dc.date.issued2007
dc.identifier.citationJournal of Engineering Research and Education, vol. 4, 2007, pages 30-40.en_US
dc.identifier.issn1823-2981
dc.identifier.urihttp://jere.unimap.edu.my
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/7448
dc.descriptionLink to publisher's homepage at http://jere.unimap.edu.myen_US
dc.description.abstractPreviously reported multiplication algorithms mainly focus on rapidly reducing the partial product rows down to final sums and carries used for the final accumulation. In this paper, an efficient approach for partial product generator is presented. The approach focuses on reducing the number of partial product rows by performing the two's complement operation even before applying partial products reduction techniques. Consequently, this directly influences the speed of the multiplication as well as the area of the circuits.en_US
dc.language.isoenen_US
dc.publisherUniverisiti Malaysia Perilsen_US
dc.subjectMultipliers (Mathematical analysis)en_US
dc.subjectMultiplicationen_US
dc.subjectAlgorithmsen_US
dc.subjectPartial product rowsen_US
dc.titleA high speed and well-structured partial product generator for parallel multiplieren_US
dc.typeArticleen_US
dc.contributor.urlrizalafande@unimap.edu.myen_US


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