Simulation on Effects of Different Types of Channel/Drain Engineering Structure on MOS Device Performance

Abstract

This final year project is aimed to analyze the effects of three different types of channel/drain engineering structure on MOS transistor performance. As a project basis, a 0.35μm process recipe from UC Berkeley is used as reference. To proceed it, the other parameters need to be retained and only the channel/drain structure is altered. The MOS structure is first designed using TSUPREM4. The channel/drain engineering structures to be designed are Lightly Doped Drain (LDD), Moderately Doped Drain (MDD) and Halo-Implantation structure. This is followed by extraction of the electrical characteristic in MEDICI. Parameters that have been extracted are threshold voltage, linear slope, off-current and the subthreshold slope. From the results, it is found that NMOS transistor with Halo Implant structure gives the best performance. The threshold voltage (Vth) extracted for the halo implant structure is of 0.2613 V with off-current of 9.1553 x 10-3 A/um. The low Vth obtained shows that only a small amount of Vg is needed to turn-on the transistor. Meanwhile, low value of off-current means that only a small amount of leakage current flows when the transistor is in the ‘off’ condition. Other parameters extracted are linear slope with value of 27.16 μA/μm-V and subthreshold slope with value of 85.28 mV/dec.