Design and Simulation of CMOS Operational Amplifier using Mentor Graphics Tool

Abstract

Today’s atmosphere and demands continue to drive operating voltages down, especially for widely used components such as the Operational Amplifier. Some of the motivations driving the market are integration, battery operated components, and biomedical instrumentation. The increased packaging densities require reduction in feature size that, in turn, reduces breakdown voltages thereby limiting the power supply. In order to ascertain low voltage and smaller in size operational amplifier, CMOS operational amplifier is preferred. In this project, the design and simulation of low power, moderate gain, and fast settling time CMOS operational amplifier consisting of three stages is implemented. The design was implemented in Mentor Graphics employing 0.35μ TSMC process technology for simulation and analysis. Finally the layout of the amplifier designed in mentor graphics IC station to perform DRC and LVS simulation. The design resulted in a complete CMOS operational amplifier that at least met and, in a few cases, exceeded the design objectives by a large margin. The notable performance areas were the output swing of +/- 1.81V, and the common mode input range of + 1.08V and -1.81V. The deviation with the calculated values is because of short channel effects. The CMOS operational amplifier is working properly within the operating voltage 2.5V.